1. Field of the Invention
The present invention relates generally to an apparatus and method for recovering the phase of a carrier signal. In particular, the present invention relates to a Phase Locked Loop (PLL), a phase detecting method for the PLL, and a receiver using the same.
2. Description of the Related Art
FIG. 1 is a block diagram of a PLL circuit according to a first conventional technology system.
Referring to FIG. 1, the PLL circuit includes a phase detector 101 for extracting a phase displacement component between an input signal xn and a feedback signal vn, a Loop Filter (LF) 102 for controlling the operational characteristics of the loop based on an error signal en received from the phase detector 101, and a Numerically Controlled Oscillator (NCO) 103 for oscillating the feedback signal vn according to the output of the LF 102.
To simplify the following description, the PLL will be described below, mainly focusing on the phase detector configured to include a multiplier.
For detection of the phase difference between the input signal xn and the feedback signal vn, the phase detector 101 comprises a multiplier 111 for multiplying the input signal xn and the feedback signal vn and outputting the resulting product signal cn, and an imaginary value extractor 112 for outputting the magnitude of the imaginary component of the product signal cn as an error signal en.
FIG. 3A illustrates the output characteristic curve of the phase detector 101 in the PLL circuit, and FIG. 3B is a diagram illustrating error signal detection in the phase detector 101.
In accordance with the above described first conventional technology system, a magnitude component (Im( ) in FIG. 3B) resulting from the projection of the input signal vn to the feedback signal vn on a complex plane is used as the error signal en.
The output en of the phase detector 101 exhibits a sinusoidal characteristic curve as illustrated in FIG. 3A. If the signal en is near an unstable point B, it is not converged to a stable point A for long (referred to as ‘hang-up phenomenon’), thereby decreasing acquisition performance. It can, therefore, be concluded that the above phase detector 101 is not viable for applications requiring fast synchronization due to its long acquisition time.
FIG. 2 is a block diagram of a PLL circuit according to a second conventional technology system.
Referring to FIG. 2, the PLL circuit includes a phase detector 201 for extracting a phase displacement component between an input signal xn and a feedback signal vn, an LF 202 for determining an oscillation frequency for an NCO 203 based on an error signal en received from the phase detector 201, and the NCO 203 for oscillating the feedback signal vn according to the output of the LF 202.
For detection of the phase difference between the input signal xn and the feedback signal vn, the phase detector 201 comprises a multiplier 211 for multiplying the input signal xn by the feedback signal vn and outputting the resulting product signal cn, a divider 212 for dividing the imaginary component Im( ) of the product signal cn by its real component, and an angle calculator 213 for calculating an arc tangent to extract an angle component from the output of the divider 212.
FIGS. 4A and 4B illustrate an error signal detecting method according to the second conventional technology system. Specifically, FIG. 4A illustrates the output characteristic curve of the phase detector 201 and FIG. 4B is a diagram illustrating error signal detection in the phase detector 201.
In accordance with the second conventional technology system, the angle between the input signal xn and the feedback signal vn on a complex plane is calculated and used as the error signal en.
The characteristic curve of the phase detector 201 is a saw function, as illustrated in FIG. 4A. Hence, if the output signal en is near an unstable point D, its value is high and thus, acquisition time to a stable point C is short. Since the phase detector 201 overcomes the hang-up phenomenon encountered with the first conventional technology system phase detector PLL 101, it is more suitable for applications requiring fast acquisition.
However, since most phase detectors using the saw function are so configured as to receive a complex value and output its angle, noise enhancement in a low Signal-to-Noise Ratio (SNR) environment decreases steady-state performance.
Moreover, when the output of the phase detector 201 is located at the unstable point D, acquisition time may be lengthened in the low SNR environment.
Further, to perform division and an arc tangent function, a look-up table may be used. For a large number of bits, however, this look-up table requires a large volume of hardware computations.
Still further, while the problem of increase in jitter in a steady state under a low SNR may be solved by decreasing a loop gain, this results in an increased acquisition time.
Accordingly, a need exists for a system and method for improving acquisition performance in an acquisition state, while preventing performance degradation in a steady state under a low SNR environment.